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<head><meta charset="utf-8"><title>NEON &amp; ABI for Armv7 / Armv8 · t-compiler/arm · Zulip Chat Archive</title></head>
<h2>Stream: <a href="https://rust-lang.github.io/zulip_archive/stream/242906-t-compiler/arm/index.html">t-compiler/arm</a></h2>
<h3>Topic: <a href="https://rust-lang.github.io/zulip_archive/stream/242906-t-compiler/arm/topic/NEON.20.26.20ABI.20for.20Armv7.20.2F.20Armv8.html">NEON &amp; ABI for Armv7 / Armv8</a></h3>

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<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/242906-t-compiler/arm/topic/NEON%20%26%20ABI%20for%20Armv7%20/%20Armv8/near/227115237" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Jubilee <a href="https://rust-lang.github.io/zulip_archive/stream/242906-t-compiler/arm/topic/NEON.20.26.20ABI.20for.20Armv7.20.2F.20Armv8.html#227115237">(Feb 20 2021 at 20:17)</a>:</h4>
<p>It's my understanding that NEON for Armv7 is "ASIMDv1" and NEON for Armv8 is "ASIMDv2". I know that these actually imply addressing the registers differently since in ASIMDv1, each 128-bit Q register is two 64-bit D registers, and in ASIMDv2 it is a set of 128-bit registers <code>v{N}</code> which can have their lower 64 bits used by various instructions. Is it safe to assume that, even if a function only included instructions assembled for the NEON ISA, that Armv7 and Armv8 NEON functions are not ABI compatible? Can instructions compiled for ASIMDv1 even run on an ASIMDv2 unit?</p>



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<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/242906-t-compiler/arm/topic/NEON%20%26%20ABI%20for%20Armv7%20/%20Armv8/near/227115595" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/242906-t-compiler/arm/topic/NEON.20.26.20ABI.20for.20Armv7.20.2F.20Armv8.html#227115595">(Feb 20 2021 at 20:22)</a>:</h4>
<p>No, you're talking about the difference between ARM and AArch64. ARM has 16 Q registers overlapping with 32 D registers. AArch64 has 32 independent Q registers which each contain a single D register.</p>



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<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/242906-t-compiler/arm/topic/NEON%20%26%20ABI%20for%20Armv7%20/%20Armv8/near/227115634" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/242906-t-compiler/arm/topic/NEON.20.26.20ABI.20for.20Armv7.20.2F.20Armv8.html#227115634">(Feb 20 2021 at 20:23)</a>:</h4>
<p>ARM and AArch64 are completely different instruction sets, you can't have both in the same program.</p>



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<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/242906-t-compiler/arm/topic/NEON%20%26%20ABI%20for%20Armv7%20/%20Armv8/near/227116275" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Jubilee <a href="https://rust-lang.github.io/zulip_archive/stream/242906-t-compiler/arm/topic/NEON.20.26.20ABI.20for.20Armv7.20.2F.20Armv8.html#227116275">(Feb 20 2021 at 20:34)</a>:</h4>
<p>Mmm, yes I did indeed say that re: the layout of registers.</p>
<p>Are you sure that it's a "can't" and not a "shouldn't" here? It is my understanding that an Armv8-A machine can nonetheless run a lot of Armv7 code in A32 mode, which is part of why I thought I'd ask to confirm. Is there a way the boundaries between the mode switches actually would stop that? And the NEON SIMD ISA and its versions seem to be somewhat orthogonal to the bitness of the rest of the unit, which is why I figured I should ask to confirm.</p>



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<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/242906-t-compiler/arm/topic/NEON%20%26%20ABI%20for%20Armv7%20/%20Armv8/near/227116651" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/242906-t-compiler/arm/topic/NEON.20.26.20ABI.20for.20Armv7.20.2F.20Armv8.html#227116651">(Feb 20 2021 at 20:41)</a>:</h4>
<p>The terminology here is a bit confusing, so I'll start by defining some terms:</p>
<ul>
<li>ARMv8 contains 2 ISAs: AArch64 and AArch32. They are completely separate, use completely different instruction encodings and run in different CPU modes. A single process can only use one ISA, it can't mix them. </li>
<li>AArch32 is an extension of the ARMv7 ISA with a few added instructions (e.g. CRC32, AES, etc). It is backwards compatible with older 32-bit ARM versions.</li>
<li>AArch64 is a complete redesign of the ISA. In some ways it is closer to MIPS/RISC-V than the traditional ARM ISA.</li>
<li>Most NEON instructions are available in both AArch32 and AArch64, however they work differently in each. Some NEON instructions only exist in AArch32 or AArch64. The instructions have different encodings and mnemonics in AArch64 and AArch32. The way they use registers is different (AArch32 has overlapping register banks, AArch64 doesn't).</li>
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<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/242906-t-compiler/arm/topic/NEON%20%26%20ABI%20for%20Armv7%20/%20Armv8/near/227117234" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Jubilee <a href="https://rust-lang.github.io/zulip_archive/stream/242906-t-compiler/arm/topic/NEON.20.26.20ABI.20for.20Armv7.20.2F.20Armv8.html#227117234">(Feb 20 2021 at 20:53)</a>:</h4>
<p>Thank you.<br>
Right, the fact that many NEON instructions exist in both aarch32 and aarch64 is kind of why I'm being nosy and trying to figure this out better, since precisely understanding the nuances here matters for what I've been writing up. :^)</p>



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<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/242906-t-compiler/arm/topic/NEON%20%26%20ABI%20for%20Armv7%20/%20Armv8/near/227123564" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Lokathor <a href="https://rust-lang.github.io/zulip_archive/stream/242906-t-compiler/arm/topic/NEON.20.26.20ABI.20for.20Armv7.20.2F.20Armv8.html#227123564">(Feb 20 2021 at 22:32)</a>:</h4>
<p>So can a program compiled for ARMv7 be run without modification as an AArch32 program?</p>



<a name="227123574"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/242906-t-compiler/arm/topic/NEON%20%26%20ABI%20for%20Armv7%20/%20Armv8/near/227123574" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Lokathor <a href="https://rust-lang.github.io/zulip_archive/stream/242906-t-compiler/arm/topic/NEON.20.26.20ABI.20for.20Armv7.20.2F.20Armv8.html#227123574">(Feb 20 2021 at 22:32)</a>:</h4>
<p>(similar to an x86 program on an x86_64 chip)</p>



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<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/242906-t-compiler/arm/topic/NEON%20%26%20ABI%20for%20Armv7%20/%20Armv8/near/227130371" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Jubilee <a href="https://rust-lang.github.io/zulip_archive/stream/242906-t-compiler/arm/topic/NEON.20.26.20ABI.20for.20Armv7.20.2F.20Armv8.html#227130371">(Feb 21 2021 at 00:41)</a>:</h4>
<p><span class="user-mention" data-user-id="224471">@Lokathor</span> Yes, when control transfers to the kernel it can choose to resume in AArch32 mode when it passes back, and as far as I am aware all instructions that a program would be compiled for Armv7 with are supported in the AArch32 mode. I am not sure what happens with the register layout change and Neon though.</p>



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<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/242906-t-compiler/arm/topic/NEON%20%26%20ABI%20for%20Armv7%20/%20Armv8/near/227130668" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Jubilee <a href="https://rust-lang.github.io/zulip_archive/stream/242906-t-compiler/arm/topic/NEON.20.26.20ABI.20for.20Armv7.20.2F.20Armv8.html#227130668">(Feb 21 2021 at 00:47)</a>:</h4>
<p>...Ah! It uses the same overlapping rules as in Armv7 apparently.</p>



<hr><p>Last updated: Aug 07 2021 at 22:04 UTC</p>
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